This invention relates generally to semiconductor devices and to a process for fabricating semiconductor devices. More specifically, this invention relates to semiconductor devices having a passivation layer and to a process for fabricating such devices.
One of the final steps in the fabrication of a semiconductor device at the wafer level is the application of a final passivation layer or coating. The final passivation layer of a semiconductor device serves as a protection layer which should be a good chemical barrier as well as a good mechanical barrier. The passivation layer protects the semiconductor device from being damaged during further handling, processing, and packaging. There are a number of properties that are ideally found in a passivation layer regardless of the type of semiconductor device to which the layer is applied. The desired properties include, for example, good moisture barrier, controlled stress so as not to impart an undesired mechanical stress to the underlying device, stable film quality under environmental changes, and good mechanical strength and hardness. In addition, the passivation layer must be capable of being processed in accordance with reasonable photo lithographic processes so that contact holes can be opened through the layer.
Some semiconductor devices place additional requirements on the final passivation layer. For example, for flash memory or other non-volatile memory technologies, the passivation layer must be UV light transparent so that the device can be erased using ultraviolet light. Even electrically alterable non-volatile memory devices are usually erased, at least initially, using UV light. The concentration of silicon-hydrogen bonds in the layer should also be as low as possible for such devices because such bonds are considered to cause reliability problems for memory devices.
There is a seemingly unending trend in the semiconductor industry to scale down device dimensions. As part of this trend the spacing between adjacent metal lines continues to decrease while the thickness of the metal line tends to remain the same or at least not to decrease proportionally with the spacing. This results in a narrowing gap between metal lines, with the gap having a large aspect ratio that is difficult to fill completely by using conventional chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) film deposition techniques. If the gaps are not filled completely, however, residue from subsequent steps may be trapped in resulting voids causing device instability and/or device failure.
In the past, passivation layers have been achieved by depositing a thick two layer film structure by PECVD. The first layer has been a layer of silicon oxide and the second, overlying layer, has been a layer of silicon nitride. In this prior art structure the silicon nitrite was used because it provides a much harder surface than does PECVD oxide. In addition to the problem of void formation, the prior art film has been unsatisfactory as a passivation layer in memory devices because silicon nitride has a low transparency for UV light and because silicon nitride contains a high concentration of silicon-hydrogen bonds.
Thus it is apparent that a need existed for an improved final passivation layer, especially for flash memory and other non-volatile memory technologies, that would overcome the problems attendant with the prior art passivation layers. A need also existed for an improved semiconductor device utilizing such a final passivation layer and for a process for fabricating such passivation layer and semiconductor device.